PERIPH_CLK2_SEL=PERIPH_CLK2_SEL_0, LPSPI_PODF=LPSPI_PODF_0, TRACE_CLK_SEL=TRACE_CLK_SEL_0, LPSPI_CLK_SEL=LPSPI_CLK_SEL_0, PRE_PERIPH_CLK_SEL=PRE_PERIPH_CLK_SEL_0
CCM Bus Clock Multiplexer Register
| LPSPI_CLK_SEL | Selector for lpspi clock multiplexer 0 (LPSPI_CLK_SEL_0): derive clock from PLL3 PFD1 clk 1 (LPSPI_CLK_SEL_1): derive clock from PLL3 PFD0 2 (LPSPI_CLK_SEL_2): derive clock from PLL2 3 (LPSPI_CLK_SEL_3): derive clock from PLL2 PFD2 |
| PERIPH_CLK2_SEL | Selector for peripheral clk2 clock multiplexer 0 (PERIPH_CLK2_SEL_0): derive clock from pll3_sw_clk 1 (PERIPH_CLK2_SEL_1): derive clock from osc_clk 2 (PERIPH_CLK2_SEL_2): derive clock from pll2_bypass_clk |
| TRACE_CLK_SEL | Selector for Trace clock multiplexer 0 (TRACE_CLK_SEL_0): derive clock from PLL2 1 (TRACE_CLK_SEL_1): derive clock from PLL2 PFD2 2 (TRACE_CLK_SEL_2): derive clock from PLL2 PFD0 3 (TRACE_CLK_SEL_3): derive clock from PLL2 PFD1 |
| PRE_PERIPH_CLK_SEL | Selector for pre_periph clock multiplexer 0 (PRE_PERIPH_CLK_SEL_0): derive clock from PLL2 1 (PRE_PERIPH_CLK_SEL_1): derive clock from PLL3 PFD3 2 (PRE_PERIPH_CLK_SEL_2): derive clock from PLL2 PFD3 3 (PRE_PERIPH_CLK_SEL_3): derive clock from divided PLL6 |
| LPSPI_PODF | Divider for LPSPI. Divider should be updated when output clock is gated. 0 (LPSPI_PODF_0): divide by 1 1 (LPSPI_PODF_1): divide by 2 2 (LPSPI_PODF_2): divide by 3 3 (LPSPI_PODF_3): divide by 4 4 (LPSPI_PODF_4): divide by 5 5 (LPSPI_PODF_5): divide by 6 6 (LPSPI_PODF_6): divide by 7 7 (LPSPI_PODF_7): divide by 8 |